Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the EEPROM device. In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode, which can be a region in the substrate. The control-gate is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode.
EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two-transistor design or a three-transistor design. A three transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a sense transistor. In a two-transistor device, the functions of read and sense transistors are combined into a single transistor. To program PLD EEPROMs, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively low voltage Vpp is applied to the drain (bit line contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bit line to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the read transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bit line and a high voltage Vpp+ is applied to the array-control-gate. Under this bias condition, the high voltage applied to array-control-gate is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode.
Efficient programming of the EEPROM cell requires a large capacitive coupling between the floating gate electrode and the array-control-gate. Improved capacitive coupling also allows programming and erasing to be carried out at reduced voltages. Additionally, during the read cycle, improved reading currents can be achieved.
The tunneling capacitor of an EEPROM memory cell is typically fabricated by defining a patterned layer of polysilicon overlying the tunnel oxide layer. The lateral extent of the capacitor is determined by the edge of a strip of polysilicon. Alternatively, a predefined tunnel oxide region overlying the substrate surface can determine the lateral extent of the capacitor. The tunnel oxide is typically fabricated by first etching an opening in a gate dielectric layer to expose a predetermined area of the substrate surface. Then, a thin layer of silicon dioxide is grown on the exposed portion of the substrate.
The processing methods used to fabricate a tunnel capacitor can affect the performance of the capacitor, which in turn, can affect the performance of the memory cell. For example, when the capacitor is defined by the edges of a patterned polysilicon layer, over time, with numerous program and erase cycles, the edges of the polysilicon slowly degrade. The edge degradation reduces the tunneling current, thus increasing the time needed to program and erase the memory cell. Further, the capacitor fabrication technique in which the capacitor edge is defined by etching a gate oxide layer and regrowing the tunnel oxide has become impractical in advanced memory devices. In advanced memory cells, the gate dielectric layer either has the same thickness as the tunnel oxide layer, or is even thinner than the tunnel oxide layer.
Accordingly, a need exists for an EEPROM device and fabrication process to produce an EEPROM device having an improved tunneling capacitor that is not susceptible to edge degradation and that does not require redundant processes techniques.